Digital sampling requires a sample clock with low jitter since the more jitter in the sample clock, the more inaccurate the timing of the sampling event. Inaccurate timing of the sampling event translates into greater noise in the sampled signal. This is particularly evident in wideband digital sampling and can be expressed by the equation:SNR=20*log(2*π*Fin*Tj)
where Fin is the sampled frequency and Tj is the sampling clock jitter For example, in order to obtain 75 dB SNR for a Fin of 70 MHz, the equation above requires a sample clock with less than 400 fs of RMS jitter.
In order to achieve this jitter performance, a sampling clock would generally need an amplitude-to noise floor ratio of −165 dbc/hz or less. This is due to the wide input bandwidth of the data converter's clock input being exposed to the noise floor power several hundred MHz away from the clock frequency. Furthermore, the noise floor of a sample clock signal can fold into the sample bandwidth of a data converter at every multiple of the Nyquist frequency. This folding essentially introduces copies of the noise into the sampled signal which further degrades the signal-to-noise ratio of the sampled signal. A clock with this low noise floor performance is relatively expensive compared to other off-the-shelf clock sources. This relatively high cost and complexity is increased even for a system requiring several synchronous data converters.
For the reasons stated above, and for other reasons stated below which will become apparent to one of ordinary skill in the art upon reading and understanding the present specification, there is a need in the art for a system and method of distributing a sample clock which provides the needed accuracy without relatively high cost and complexity.